Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC

DDR, System Verilog, IP Verification, HBM, Design Verification, Environment Development, Functional Verification, Memory IP, Uvm, GDDR, Test Plan Generation

power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies