THE ROLE:

The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICs that meet Engineering, Business and Customer requirements.

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

THE PERSON:

AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions.

KEY RESPONSIBILITIES:

Implementing RTL to GDS2 flow
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
Provide technical support to other teams

PREFERRED EXPERIENCE:

5+ years of professional experience in physical design, preferably ASIC designs.
Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow.
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Strong analytical/problem solving skills and pronounced attention to details

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Sr. Silicon Design Engineer

Sr. Silicon Design Engineer (AECG ASIC Physical Design)