Verilog, Logic Design, on-chip memory controller, verification processes, design simulation, Design Architecture, Schematics, RTL

Linux Environment, Perl, Version Control Systems, Verilog, System Verilog, Python, Tcl, SOC tools, DFT technologies, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Synopsys Design Compiler, Questa CDC, VCS simulation

Linux Environment, Version Control Systems, Perl, Verilog, System Verilog, Python, Tcl, SOC tools, DFT technologies, UPF, Rtl Design, primetime, Cadence Conformal, spyglass, Synopsys Design Compiler, Questa CDC, VCS simulation

Verilog, Soc, Timing Closure, IP integration, Synthesis, linting, systemverilog, ASIC, Digital Design, gate-level simulations

Perl, ASIC, Digital Design, Sta, Circuit timing, Rtl Design