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Showing 3 jobs
Skills:
C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Debug features, UPF support, Low Power features, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning
Skills:
C, Vcs, Jtag, Perl, Verilog, Python, Tcl, UPF support, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning, Low Power technologies
Skills:
Verilog, Soc, Timing Closure, IP integration, Synthesis, linting, systemverilog, ASIC, Digital Design, gate-level simulations
