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ASIC Design Verification Engineer | UVM | Exp 8+ Years

Cisco Live
Bengaluru, India

Skills:

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Early Applicant

ASIC Design Verification Engineer | UVM | Exp 8+ Years

Cisco Home
Bengaluru, India

Skills:

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Early Applicant

Staff ASIC Design Verification Engineer

Qualcomm
Q
Bengaluru

Skills:

hardware engineering , System Verilog, formal verification, Design Verification, Uvm, ASIC Design

Early Applicant

SMTS Silicon Design Engineer ( ASIC Security Design Verification Engineer )

AMD
Bengaluru

Skills:

hardware engineering , System Verilog, ASIC Security Knowledge, Rtl Design

Early Applicant
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