Computer Architecture, C, Makefile, Hdl Programming, Digital Logic Design, Perl, Verilog, Ruby, Python, System Verilog, UNIX Software Environment, AI Tools, Logic Simulation, Functional Verification, Simulation and Debugging

Perl, Python, Tcl, Calibre, Xcelium, Synopsys CustomSim, Verilog-A AMS, AMS Designer, Cadence Virtuoso, systemverilog, Spectre

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Test Plans, Test Cases, SoC protocols, SoC Verification, formal verification tools, Uvm, emulation platforms, systemverilog, low-power verification, coverage models

snoops, Coverage, SystemVerilog UVM assertions, ARM AMBA CHI, Ordering, caches, cache coherency concepts, MESI, SystemVerilog UVM, load store atomics, multicore CPU architectures, MOESI

python, perl, SV test benches, Gate level simulations, SDF annotation, VMM, constrained random verification, Uvm, functional coverage, C-reference models

scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents