Verilog, Static Timing Analysis, System Verilog, Spyglass CDC, Glitch analysis, SDC development

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification

Networking Protocols, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, ASIC Design, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Verilog, Python, Perl, Gdb, SOC design, Indago, Cadence