redhawk , Shell, Python, Tcl, SC CADENCE, semiconductor device physics, Voltus, Calibre, EDA Tools, EMIR tool flows, Reliability verification, SVRF, ESD PERC design rules

Static Timing analysis, Perl, Tcl, Clock Planning, Implementation PnR Signoff, Parasitic Extraction, Floor Planning, Power Plan, Digital place and route, Constraint development, Place And Route, High speed SoC designs, Clock Tree Synthesis

UNIX, Perl, System Verilog, Python, Tcl, primetime, Fusion Compiler, ICC2, Formality, UPF, Innovus, VHDL, EDA Tools, Synopsys Design Compiler, Linux Shell, low-power design techniques

strace , Github, Golang, Machine Learning, C, CSS, Gdb, PostgreSQL, Bash, Dns, HTML, Smtp, Javascript, Linux, Perl, PERL, MySQL, Tls, Python, AJAX, Ai, AI APIs, Large Language Models

strace , MySQL, AJAX, C, Dns, Github, HTML, Gdb, Golang, CSS, Linux, Machine Learning, Tls, Bash, Python, PERL, PostgreSQL, Smtp, Javascript, Large Language Models, Ai, AI APIs

Tcl, Perl, Innovus, RDL bump planning, IR-drop, Fusion Compiler, Calibre, Reh-hawk sign-off, Red-Hawk

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

Pvs, Tcl, Python, Perl, LVS, Xl, Analog layout design, DRC, Calibre, R3D, PEX, virtuoso

Usb, Tcl, Verilog, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, static RTL checks, Cadence Mentor simulation suites, Xilinx Vivado, systemverilog, Synthesis, Axi, FPGA design tools, Intel Quartus, low power design techniques, AMBA bus protocols, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures