power optimization , Perl Scripting, Physical Design Flow, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, Floor-planning, Place And Route, Synopsys ICC2

Tcl Scripting, Cadence Genus, UPF, LEC, Synopsys Fusion Compiler, Conformal, VCLP, RTL synthesis

ASIC physical implementation, RTL to GDSII design flow, Timing constraints and sign-off, Scripting in Perl/Tcl/Python, Fusion Compiler