C, System Verilog, IP verification, Uvm

Jtag, Pcie, Perl, System Verilog, Python, Tessent Embedded Analytics, UltraSoC, UVM methodology, Design for Debug, High speed USB, RISC Debug Architectures

Test Bench development in System Verilog, Verification methodologies such as UVM, NAND Flash memory design, Understanding of StarRC Calibre parasitic extraction flow

Verilog, Silicon Validation, BSEE or MSEE, VHDL, Mixed-signal circuits, Product characterization, Automated characterization flows, Characterization of SoC processors

arm architecture , C, Ethernet, Pcie, Usb, DDR, assertion-based formal verification tools, Uvm, SoC DV execution, HBM, hardware emulation support