Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, micro-architecture, System-Verilog, SOC design, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi

Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

Logic Design, Verilog, Sta, Synthesis, block and top-level timing constraints, Power product design, mixed signal integrated circuits, Scan Insertion, Timing Analysis, design constraints, ATPG generation, synthesis scripts, RTL Coding, micro-architecture, System-Verilog

Technical Leadership, System Architecture, Cross-Functional Collaboration, Methodology Expertise, Customer Engagement, Multi-Domain Expertise