Verilog, Oops Concepts, scripting and tool development using Perl, VCS or equivalent simulation tools, debug tools like Debussy GDB, VMM, Uvm, systemverilog

Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, industry-standard simulation tools, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage

Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, MIPI, Axi, APB, CXL, AHB, SoC Verification