Perl, Python, SV – UVM Assertions based verification, RTL debug skills, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

rtl verification , simvision , Pcie, Debugging, Version Control Systems, Python, Usb, Git, Perl, AI ML fundamentals, anomaly detection, Uvm, FPGA-based verification environments, testbenches for constrained-random and metric-driven verification, vManager, EDA Tools, coverage prediction, UFS, ML techniques for regression triage, failure clustering, waveform-debug tools, systemverilog, eMMC, Cadence NCSim, DDR4, SVA

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Vcs, Ovm, Usb, Tcl, System Verilog, Ethernet, Python, Pcie, Perl, DDR, Uvm, UFS, MTI, AMBA, MIPI-I3C, NC, VMM

Verilog, random stimulus, VMM, assertion-based verification, Uvm, functional coverage, systemverilog, advanced verification methodologies

Perl, Networking, hw design, Uvm

simvision , Cmake, Shell, Perl, Python, Verdi, Cadence Xcelium, JasperGold, Palladium, make, Uvm, UPF, systemverilog, Siemens Questa, Synopsys VCS, Zebu, DVE, Veloce, PropCheck, CPF, VC Formal, SVA