Apis, middleware, AI copilots, AI assisted testing analysis tools, automated documentation tools

Timing Closure, Verilog RTL design, FPGA Design Flow, digital logic design using FPGAs, Timing Analysis, debugging and problem-solving skills

Perl, System Verilog, Python, analog mixed-signal AMS, formal verification, VHDL, Uvm, digital mixed-signal simulations

AWS, Splunk, Cloudformation, logging tools, Devops, Terraform, Appdynamics, AI-assisted solutions, CI CD tooling

C Programming, Python, Security practices in firmware software development, Linux auxiliary bus driver model, Out-of-band device management, NVMe host or target driver development, RDMA RoCE, DRAM architecture, Linux kernel module development, Multi-function PCIe device architectures, GPU host-side driver development, PCIe protocol expertise, MCTP OpenBMC stacks, CXL Compute Express Link, ARM SoC architecture

serial protocols , Boot Loaders, C Programming, CPU architecture, Android environment, SOC systems knowledge, validation methodologies, microprocessor concepts, DRAM interface signal analysis

static timing analysis, debug SDF annotation issues, circuit characterization timing libraries, System Verilog Assertions, Uvm, transient analysis, Verilog MOS switch level models, Gate level simulations with SDF back annotation, latch based designs and their timing requirements, timing arcs, zero delay unit delay and path delay simulations, DC analysis, HBM Staff Circuit Memory Verification Engineer, circuit simulation with spice simulators, debugging Gate level simulation failures, deciphering circuit behavior from schematics, netlist simulation

Dashboards, Reporting Tools, Integrations, Sql, Data hygiene, AI-assisted personalization, Excel Sheets, RevOps Infrastructure, Automations, Pipeline generation engines, Revenue Tech Stack, data reporting

Synthesis, RTL code in Verilog, SoC integration, Timing Closure, RTL logic design, micro-architecture specifications, Verification, timing optimization, assertions coverage analysis