Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Git, Confluence, Perl, Jira, Python, CPF, Uvm, UPF, systemverilog

snoops, Coverage, SystemVerilog UVM assertions, ARM AMBA CHI, Ordering, caches, cache coherency concepts, MESI, SystemVerilog UVM, load store atomics, multicore CPU architectures, MOESI

scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents

scoreboard , test environments , Test Cases, C, Shell, Soc Architecture, Verilog, Agents, Mixed signal designs, Verification testbenches, Debugging RTL and Gate simulations, Verification methodology, Monitors, Regression systems, Testbenches, Sequencers, Industry-standard simulators, Revision control systems, Directed and constrained random verification methodology