C, Gdb, Verilog, Python, Scripting Languages, Synthesis, SOC development, Rtl Design, Cadence, RTL Build, Design Automation, Timing Closure, Verification, ASIC architecture, Physical Design, Dft, Micro-Architecture, Indago

Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, Debug architecture, Axi, SoC Clocks, SDCC, APB, RST, SOC design, AHB, System-Verilog

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design

Usb, System Verilog, Jtag, Ethernet, Python, Pcie, Perl, TSN, UVM methodology, SoC architecture verification, scripting in Linux Unix environments, High speed USB, Design for Debug, ARM based SoC verification