Perl, Verilog, Python, Makefiles, RTL Build flows, SoC Clocks, System-Verilog, Synthesis, RST Debug architecture

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

Computer Architecture, Timing Constraints, digital RTL design, RTL microarchitecture, architecture experience on advanced SoCs, clocking and reset methodologies