C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Synthesis, Ethernet networking protocols, RTL checks, RTL Coding, lint CDC checks

Vcs, Gdb, micro architecture definition, RTL coding using Verilog, scripting knowledge, Simulation Tools, Synthesis, interconnect design, LINT, debug tools like Debussy, design and verification tools, cache controller design

Vcs, Gdb, micro architecture definition, RTL coding using Verilog, scripting knowledge, Simulation Tools, Synthesis, interconnect design, LINT, debug tools like Debussy, design and verification tools, cache controller design

Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

Python, Low power estimation, Timing Closure, Synthesis, RTL quality checks, ASIC Design, Electrical/Computer Engineering

Perforce, static timing analysis, Shell, Verilog, Version Control Systems, Scripting Languages, Python, Git, Perl, Tcl, cdc, Simulation, formal verification, EDA Tools, Rtl Design, Synthesis, SoC Architecture Design, LEC, AMBA protocols, systemverilog, Axi, APB, LINT, AHB, SoC Integration

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Bus Protocols (AHB/AXI/NOC), low power design, formal verification, Verilog/SystemVerilog, Spyglass CDC/Lint, Rtl Design