Verilog, LINT, cdc, Micro-architecture development, Functional Safety concepts, systemverilog, Synthesis checks, RDC, ASIL requirements, RTL design and integration, ISO 26262, Safety analysis methodologies

Verilog, Sta, Synthesis, cdc, Dft, ATPG, RTL Coding, LINT, SDC creation, systemverilog

System Verilog, Pcie, CXL, RTL coding Verilog, AMBA controller IP, FPGAs

Pcie, Verilog, Ethernet, Debugging, Scripting, Python, Tcl, UCIe chiplet interconnects, digital design fundamentals, high-speed IO protocols, systemverilog, Rtl Design, CXL, micro-architecture, low-power design techniques

Perl, Verilog, Python, Synthesis, processor design, low power design techniques, arithmetic units, Chisel, memory hierarchies, design for testing, timing power analysis, systemverilog, Asic Design Verification, accelerators, micro-architecture, bus architectures

CDC RDC closure, spyglass, RTL refactoring, Formal verification methods, Integration testplans, Synthesis flows, ASIC RTL design

Noc, Gpu, Perl, Verilog, Performance Modeling, Python, Tcl, Siemens flows, high-bandwidth memory systems, Cadence, systemverilog, architecture exploration, Rtl Design, Axi, NPU, APB, EDA Tools, Synopsys, AHB