Usb, DDR, Pcie, Verilog, Ethernet, LINT, Sta, Synthesis, cdc, UCIe, systemverilog, spyglass, VHDL, formal checking, RDC, HBM

catapult , Vcs, Ecos, Verilog, System Verilog, spyglass, LINT, Timing Analysis, Synopsys DC, cdc, Rtl Design, Verdi, VHDL, Stratus, Xcellium, SDC, Dft, Magillem, low power design methodologies

C, Makefile, Perl, Python, Tcl, Systemc, ARM bus protocols, Root of Trust verification, secure processor verification, cryptographic IP verification, formal verification tools, assertion-based verification, Uvm, regression debug, test bench architecture, directed testing, coverage-driven verification, systemverilog, constrained-random verification, security property checking, SoC protocols, EDA Tools

Verilog, RDC, LINT, ISO 26262, Safety analysis methodologies, Functional Safety concepts, RTL design and integration, systemverilog, ASIL requirements, Synthesis checks, cdc, Micro-architecture development