Verilog, random stimulus, VMM, assertion-based verification, Uvm, functional coverage, systemverilog, advanced verification methodologies

Perl, Networking, hw design, Uvm

simvision , Cmake, Shell, Perl, Python, Verdi, Cadence Xcelium, JasperGold, Palladium, make, Uvm, UPF, systemverilog, Siemens Questa, Synopsys VCS, Zebu, DVE, Veloce, PropCheck, CPF, VC Formal, SVA

hardware engineering , Java, Dsp, C++, Sql, Jenkins, Linux, Debugging, Makefiles, Design Verification, Ip, systemverilog, Critical Thinking

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Perl, Verilog, Python, Tcl, quartus, VHDL, Vivado, FPGA IP Design Validation, Vlsi Design, systemverilog