logic bist , static timing analysis, UNIX, Jtag, Linux, Verilog, Synthesis, DFT techniques, Scan Insertion, memory BIST, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan

logic bist , boundary scan , simulation and verification flow, clock control block, DFT compression, silicon debug, DFT technologies, scan chains, fault modeling, DFT strategy and architecture, IP integration, DFT specification definition, DFT design and verification, DFT architecture, die level DFT validation, silicon bring-up, ASIC DFT synthesis, TAP controller