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SMTS SILICON DESIGN ENGINEER 

 

The Role

AMD is seeking an experienced **Static Timing Analysis (STA) Lead** to join our high-performance Cores team. This role will be responsible for ensuring timing closure and optimization of next-generation CPU/APU designs operating at industry-leading frequencies. The ideal candidate will have deep expertise in STA methodologies, timing marginings, and yield analysis for advanced process nodes.

THE PERSON: 

As an STA Lead in the AMD Cores team, you will play a critical role in delivering high-frequency, power-efficient processor designs that push the boundaries of performance. You will work closely with RTL design, physical design, and verification teams to ensure robust timing closure across multiple process corners and operating conditions.

 

KEY RESPONSIBILITIES: 

11+ years of experience in Static Timing Analysis for high-performance digital designs
5+ years** working on CPU, GPU, or high-frequency ASIC designs
Proven track record of leading timing closure for complex SoCs through multiple tapeouts

Timing Closure & Analysis

Lead static timing analysis for high-frequency CPU/APU cores running at 4+ GHz
Perform comprehensive timing signoff across all PVT corners (SS, TT, FF, FS, SF) and voltage/temperature combinations
Drive timing closure from RTL freeze through tapeout, ensuring all setup, hold, and transition violations are resolved
Develop and maintain timing constraints (SDC) for complex clocking architectures including multi-mode, multi-corner scenarios
Analyze and optimize critical paths to achieve frequency targets while minimizing power impact
Perform timing ECO (Engineering Change Orders) and coordinate with physical design teams for implementation

Timing Marginings & Variability Analysis

Define and implement timing margins for process variation, voltage droop, aging, temperature gradients, and OCV (On-Chip Variation)
Conduct **statistical timing analysis (STA/SSTA)** to account for process variation and ensure robust yield
Perform **AOCV/POCV/SOCV** analysis for advanced nodes (5nm, 3nm and beyond)
Develop methodologies for **IR drop analysis** and voltage-aware timing closure
Analyze **aging effects** (NBTI, HCI, EM) and define appropriate timing guardbands
Work with characterization teams to define **derating factors** and timing models

Yield Analysis & Optimization

Collaborate with yield engineering teams to analyze timing yield and identify sensitivities
Perform path-based analysis (PBA) and graph-based analysis (GBA) to reduce pessimism
Conduct Monte Carlo simulations and corner analysis to ensure robust timing across process spread
Identify and optimize timing-critical structures to improve manufacturability
Drive binning strategies based on frequency and voltage guardband analysis

 

PREFERRED EXPERIENCE: 

Physical Design Exposure

Physical design experience (synthesis, place & route, or timing closure)
Understanding of placement optimization for timing improvement
Knowledge of routing impacts on timing (via count, metal layer selection, wire models)
Experience with floorplanning and its impact on timing
Familiarity with physical design tools: Synopsys Fusion Compiler, Cadence Innovus/Genus
Understanding of buffer insertion and gate sizing strategies
Knowledge of pin assignment and I/O timing closure

Clock Tree Synthesis (CTS) Recipes

Experience **defining CTS recipes** and specifications for clock tree builders
Deep understanding of **CTS algorithms**: H-tree, X-tree, fishbone, mesh
Knowledge of **clock buffer selection** and sizing for skew/latency optimization
Experience with **useful skew** implementation and optimization
Understanding of **clock concurrent optimization (CCOpt)**
Familiarity with **clock tree QoR metrics**: insertion delay, skew, transition, power

Additional Preferred Skills

Experience with **Synopsys tools**: Design Compiler, IC Compiler II, PrimeTime SI/PX
Knowledge of **machine learning** applications in timing prediction and optimization
Familiarity with **FinFET** and **Gate-All-Around (GAA)** transistor timing characteristics
Understanding of **3D IC** and chiplet-based timing analysis
Experience with **timing correlation** studies between STA and SPICE
Knowledge of **standard cell characterization** and timing library generation

 

ACADEMIC CREDENTIALS: 

Bachelors or Masters degree in computer engineering/Electrical Engineering

CTERR1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.

STA Lead - CPU Team