C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Verifying sophisticated blocks clusters and top level for ASIC, Palladium, Veloce