Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Your Impact

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications

Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10-12 years of experience.
Knowledge of the latest innovative trends in DFT, test and silicon engineering.
Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Experience working with Gate level simulation, debugging with VCS and other simulators.

Preferred Qualifications

Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
Strong verbal skills and ability to thrive in a multifaceted environment
Scripting skills: Tcl, Python/Perl.

Why Cisco

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

About

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DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years