Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, IP subsystem SoCs, congestion control, systemverilog, constrained-random verification, packet processing, Verification, standard IP components