Shell, Perl, Python, Tcl, advanced Design languages, SOC IP Integration, Rtl Design

coverage closure, Gate level simulations, real number modeling, System Verilog UVM, Vplan regression

Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Asynchronous interface, Synthesis, Axi, timing concepts for ASIC, APB, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog