rc extraction , Programming Skills, automation, full-custom circuit layout verification, mixed signal analog high speed layout, advanced semiconductor technology process and device physics, Cadence Virtuoso, Circuit Design, EMIR analysis

arm architecture , Encryption, Ecc, concurrency, testplan development, Compression, CHI, SOC power management, latency, clock reset, DDR Interconnects, system level aspects, Uvm, Design, Coherency bus interconnects, micro-architecture, interconnect protocols, IP architecture, Ace, bandwidth, Axi, ACE-Lite, AHB, Verilog logic design principles

POL design, Simplis, power management applications, Inductors, capacitors, regulator architectures, IC block level modelling, digital controllers, Control System Design, Gate Drivers, Pspice

congestion management , Tcl, Python, Perl, Synopsys ICC2, Cadence Innovus, clock gating, clocking methodologies, primetime, physical implementation, power-aware physical implementation, clock domain partitioning, SoC-level floorplanning, clock tree architecture, Timing Closure, low-power design techniques

regulators , Verilog, Matlab, HSIM, deep sub-micron CMOS technologies, TX, IC design CAD tools, RX, high-speed design techniques, Spectre, DACs, PLLs, Spice, Filters, lab testing skills, ADCs, Bandgap bias circuits

Perl, Verilog, System Verilog, Python, Jasper, JEDEC NAND interface standards, NCSim, VS Formal, Rtl Design, IMC, Verdi, netlist integration, mixed-signal design concepts, Xcellium, IEV, NAND flash memory technologies, formal verification techniques, synthesis tools