Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP-level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, RTL code, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware, testbenches processes and flows

C, Usb, Makefile, Windows, Shell, Linux, Perl, Pcie, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, acceleration HLS tools, Graphics pipeline knowledge, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM