Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, Dft, FPGA and emulation platforms, RTL design concepts, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

C, Perl, Vcs, Python, Xcelium, Uvm, systemverilog

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4

Rtos, Bash Scripting, Assembly Language, Python Programming, Emulation pre-si environment, JTAG tool debuggers, Linux kernel internals, DFT and Modem characterization, ARM SoC architecture, C Language

DVCS e.g. Git, Dom, Xpath, Gcc, Xslt, Sql, Linux, Xml, Javascript, Python, System Verilog, Assembly languages, SGE or other DRMS, Uvm, Web programming – HTML, LLVM, SVA

arm architecture , Usb, Gerrit, Uart, Spi, Silicon Validation, Git, Embedded C Programming, Debugging, I2c, Device Driver Development, low-level embedded systems, i2s, eMMC, Bare-metal programming, SoC bring-up, root-cause analysis

static timing analysis, UNIX, Linux, Perl, Verilog, Tcl, CAD software scripts, Synthesis, DFT RTL integration, Scan Insertion, Timing Analysis, ATPG verification, waveform debugging tools, Rtl Design, EDA tools methodology, test pattern generation, DFT design-for-test, equivalency checking, DFD design-for-debug, verification of DFx logic, DFT documentation, c-shell