Ant, Mentor Calibre, Memory analog layout design, floorplanning, high speed GHz circuit design, LVS, Latch-up, CMOS process geometries, signal and clock shielding, EMIR, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, DRC, signal flow planning, isolation techniques, Cadence Virtuoso, Reliability

Parasitic effects, LVS DRC PEX EMIR verification flows, xACT, Reference circuits, Calibre DRC, Bandgap Oscillators, StarRC