power integrity , Routing, Perl, Python, Tcl, Physical Sign off, Chip finishing, Metal fill, Tapeout checks, Clock Trees, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Placement, Timing Closure, Equivalence Check, Synthesis Constraints

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2