C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

power integrity , Tcl, Routing, Python, Perl, Physical Sign off, Synthesis Constraints, Physical Verification, Equivalence Check, Metal fill, RTL2GDS flow, Signal Integrity, Chip finishing, Physical Design, Power Distribution Network, Clock Trees, Tapeout checks, Placement, Floorplans, Timing Closure, Sealring

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management