Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

Logic Design, Verilog, Sta, Synthesis, block and top-level timing constraints, Power product design, mixed signal integrated circuits, Scan Insertion, Timing Analysis, design constraints, ATPG generation, synthesis scripts, RTL Coding, micro-architecture, System-Verilog

Tcl, FPGA Design, System Verilog, C, Python, Unix Shell Script, Perl, Vcs, Synthesis, RTL validation, LINT, Synopsys simulators

Linux, Python, Digital Flows, DV Methodologies, Design Automation, EDA Tools