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Senior Staff Engineer, RTL ASIC Design

Marvell Technology, Inc.
M
Bengaluru, India

Skills:

Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

Early Applicant

Senior Staff Engineer, RTL ASIC Design

Marvell Technology - Multimedia Solutions Business
Bengaluru, India

Skills:

Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, NoC architecture, USB standards

Early Applicant

Senior Staff Engineer, Static Timing Analysis (STA) Lead

SiFive
Bengaluru, India

Skills:

synopsys primetime , Synopsys FusionCompiler, AI ML Integration, Advanced Node Experience, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, Advanced Clocking

Early Applicant

Senior Staff Engineer Design

Infineon Technologies
Bengaluru, India

Skills:

Test Plans, Uart, Pcie, LINT, power analysis, RTL implementation, timing closure verification, Digital Design, coverage closure, WiFi MAC architectures, IP enhancements, WiFi 802.11 standard, functional coverage, CDC checks, SDIO

Early Applicant

Senior/Staff- Engineer: Post Silicon- Bring Up

Cerebras Systems
Bengaluru, India

Skills:

Jenkins, Github, Git, Pytest, C, Verilog, Python, System Verilog, Git actions

Early Applicant
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