Verilog, Static Timing Analysis, System Verilog, Spyglass CDC, Glitch analysis, SDC development

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification

Fpga, Rtl Design, silicon bring-up, Microarchitecture, Verilog/System Verilog, IP integration, Quality Checks, ASIC Design