Calibre, Analog Layout, Mixed signal layout, DRC, Custom Layout, Chip level integration, Reliability concepts, virtuoso, Physical Verification, LVS, CAD Tools

DRC, LVS, semiconductor fundamentals, Parasitic Extraction, Cadence Virtuoso, ERC, precision analog layouts, analog layout design, CMOS technology

Python, Cadence Virtuoso, EMIR, chip assembly techniques, LVS, AMS Layout Verification flows, DRC, Skill

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

Parasitic effects, LVS DRC PEX EMIR verification flows, xACT, Reference circuits, Calibre DRC, Bandgap Oscillators, StarRC

Mentor Graphic Caliber, Cadence VLE, LVS, DRC, Antenna quality check

Ant, Mentor Calibre, floorplanning, high speed GHz circuit design, LVS, 7nm and below CMOS process geometries, Latch-up, signal and clock shielding, EMIR, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, DRC, isolation techniques, signal flow planning, Cadence Virtuoso, Reliability

Ant, Mentor Calibre, Memory analog layout design, floorplanning, high speed GHz circuit design, LVS, Latch-up, CMOS process geometries, signal and clock shielding, EMIR, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, DRC, signal flow planning, isolation techniques, Cadence Virtuoso, Reliability