C, Spi, Silicon Validation, Synplicity, Verilog, Uart, Embedded Software, JESD204B, JESD204C, Board level debug, Oscilloscopes, Synthesis Placement constraints, Timing Closure, DisplayPort, VHDL, PMA features, STA constraint definition, digital analyzers, Debug, USB3.2, AMBA protocols, SERDES architecture, Failure Analysis, integrated logic analyzers, HDMI, protocol exercisers, Modelsim, I3C, high-speed serial communications protocols

C, Verilog, System Verilog, AI tools, SoC UPF power aware verification, Uvm, DFx DFT infrastructure functional verification

Perl, Python, formal verification, property checking, RTL integration, Uvm, systemverilog

rtl development , Embedded C, Verilog, Iar, Jlink, Jtrace, Microsemi Libero, Xilinx Ise, altera quartus, systemverilog, Altera Signaltap, VHDL, Synopsys Identify, Libero SoC, Modelsim, Xilinx Chipscope

Git, Shell, Verilog, Python, Tcl, VHDL, Xcelium, Uvm, systemverilog, Xilinx Vivado

Verilog, FineSim, Verification strategy, Hspice, Design Verification, PrimeSim, Uvm, systemverilog, Digital and analog simulation tools

Mac, Switch, Pcie, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, verification tools for simulation and debug, Uvm