PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

Verilog, Tcl, ASIC design flow, low-power techniques, DFT Design for Test, UPF Unified Power Format, primetime, Synopsys Design Compiler NXT DCnext, Fusion Compiler, Formality, systemverilog, MCMM flows

Logic Design, Circuit Design, Physical Verification, Industry-standard tools in semiconductor design, Physical Design, Design Methodologies, Rtl Design

Static Timing Analysis, physical design methodology, power supply management, Eco, Signal Integrity, power gating

Routing, Physical Design Methodologies, Tcl tool scripting, RTL-to-GDSII implementation, DDR design knowledge, primetime, Placement, Calibre, Genus, Innovus, floorplanning, MultiTap-CTS

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Physical Design, Vlsi, digital circuit design