Perl, Shell scripting, Python, Jasper Gold, Vmanager, Xcelium, Cadence simulation tools, UVM methodologies

rtl verification , Jenkins, Perl, Bash, Python, CDC checkers, AI ML techniques, Uvm, systemverilog, formal verification, CI methodologies, linters, csh, Verilog simulators

boundary scan , Jtag, power-on self-test, pre-Si testcases, clock control verification, memory BIST, Uvm, ATE correlation, SSN, systemverilog, compressed scan, Dft, DV, agentic AI flows, formal verification methods, silicon bring-up

DV Ip Verification

Debugging, Uvm, Mixed-Signal Verification, systemverilog

Vcs, Perl, Python, Tcl, Verdi, XSIM, AMBA protocols, Uvm, systemverilog, Axi, DVE, APB, Questa, AHB

System Verilog, Building test benches from scratch, Data path verification performance tests, ASIC verification using UVM, Gate level simulation