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Showing 4 jobs
Skills:
Soc Architecture, Debugging Tools, Perl, Verilog, Python, Tcl, interface standards, memory protocols, Simulation Tools, Palladium, Uvm, systemverilog, Rtl Design, VHDL, Zebu, Veloce, emulation platforms
Skills:
Soc Architecture, Debugging Tools, Perl, Verilog, Python, Tcl, interface standards, memory protocols, Palladium, Simulation Tools, Uvm, systemverilog, Rtl Design, VHDL, Zebu, Veloce, emulation platforms
Skills:
Soc Architecture, Debugging Tools, Perl, Verilog, Python, Tcl, interface standards, Simulation Tools, Palladium, memory protocols, Uvm, systemverilog, Rtl Design, VHDL, Zebu, Veloce, emulation platforms
Skills:
C, Perl, System Verilog, Python, Tcl, Cadence Palladium, Mentor Veloce, Synopsys ZeBu, Uvm, RTL partitioning, SVA
