RTL code in Verilog, Synthesis, SoC integration, Timing Closure, RTL logic design, micro-architecture specifications, Verification, timing optimization, assertions coverage analysis

Verilog, Scripting Languages, System Verilog, LINT, Sta, power analysis, SoC design flows, RTL integration, Digital Design, Rtl Design, Synthesis, CDC methodologies, asynchronous design concepts

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, automating workflows in a distributed compute environment, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, simulation profile efficiency improvement, UVM based verification frameworks

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Ruby, System Verilog, Ethernet, Perl, Pcie, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, TLM, simulation profile efficiency improvement, UVM based verification frameworks

C, Systemc, Windows, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Pcie, Perl, acceleration HLS tools, debugging firmware and RTL code using simulation tools, Graphics pipeline knowledge, IP level ASIC verification, automating workflows in a distributed compute environment, AXI ACE Protocols, UVM testbenches, TLM, UVM based verification frameworks, simulation profile efficiency improvement

Static Timing Analysis, UPF techniques, LINT, debug techniques, FPGA development, design closure, RTL and gate-level simulations, systemverilog, cdc, Verification, mixed-mode simulations, RDC, RTL implementation

Synthesis and Place & Route (DC, ICC2/FC), Design for Test (DFT) and ATPG, Asic Physical Design, DDR and HBM PHY implementation, Pt, FinFET technology experience