Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Fpga, Usb, Python, Pcie, Perl, Emulation, directed constrained-random tests, Uvm, AXI4, coverage driven verification, Test Bench, verification methodologies, systemverilog, transaction level modeling, AMBA, MIPI, formal verification

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog