bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, congestion control, SoCs, systemverilog, constrained-random verification environments, packet processing, Verification, standard IP components

snoops, Coverage, SystemVerilog UVM assertions, ARM AMBA CHI, Ordering, caches, cache coherency concepts, MESI, SystemVerilog UVM, load store atomics, multicore CPU architectures, MOESI

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4

Fpga, hardware emulation, simulation platforms, IEEE 1500, verification methodologies, IEEE 1149.1, Palladium, Uvm, systemverilog

Shell, Perl, Vcs, Python, Xcelium, QuestaSim, Uvm, systemverilog

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

Debugging, Perl, Python, Prototyping environments, Test plan development, Test bench infrastructure, Coverage driven verification, Uvm, systemverilog, Assertions, Directed constrained-random tests, RTL development environments, Emulation, Simulation

Unix, Unix Shell Scripts, Perl, Python, make, Uvm, systemverilog