General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Preferred Qualifications:

Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science
Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role
High level of proficiency in Tcl as well as Python
Experience with automation
Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
Experience with advanced technology nodes (5nm or lower)
Solid understanding of digital design, timing analysis and physical verification
Strong user of industry-standard place-and-route tools such as Cadence Innovus
Proven track record of managing and regressing place-and-route flows

Principal Duties and Responsibilities:

Develop, integrate and release new features in our high-performance place-and-route CAD flow
Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
Maintain, support and debug implementation flows, and resolve project-specific issues
Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA.
Work with EDA vendors to define roadmap and to resolve tool issues

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