layout verification , automation, AI tools, EM, Ir, auto placement and route tools, LVS, Totem checks, Latch up, Layout Design, Antenna Shield Matching, DRC, digital block layout, skill coding

STA tools - Tempus, Static Timing Analysis, Spice to STA correlation, Physical Verification DRC LVS DFM, primetime, Placement of hard macros, Clock-tree synthesis, Routing timing optimizations, Hierarchical designs, Floorplan design, Low Power implementation, Parasitic Extraction, Congestion reduction techniques, Timing analysis validation and debug, PCIe timing closure

Test Engineering, Automation Solutions, Robotics, Machine Vision Systems, Failure Analysis

Github, Test Cases, Test Execution, Api Testing, Sql Queries, Javascript, Gitlab, Selenium, Oop Concepts, data structures, Python, Azure DevOps, Java, Test Scenarios, Test Plans, Appium, Jira, Sdlc, Git, Stlc, automation testing concepts, manual testing concepts, REST fundamentals, HTTP methods, Playwright, defect lifecycle, status codes, Cypress