arm architecture , C, Usb, DDR, Pcie, Ethernet, Systemc, SoC DV execution, hardware emulation support, Uvm, assertion-based formal verification tools, HBM

arm architecture , DDR, Usb, C, Pcie, Ethernet, hardware emulation support, SoC DV execution, assertion-based formal verification tools, HBM, Uvm

C, Perl, Pcie, Vcs, Python, Tcl, Debug Skills, PA Exerciser, LA PCIe Switches, LPDDR, Viavi Lecroy Hardware

Jtag, Perl, DFT IP integration, MBIST, Analog Macro tests, timing SDF simulations, coverage improvement techniques, test mode timing constraints, block level and chip STA flows, ATPG, chip tape out, Fault Models, debug on ATE, Cadence Tessent tools, post-silicon bring up, Scan, test point insertion, gate level simulation, scan insertion techniques, Memory BIST generation