Design validation, Parasitic modeling, Tape-out revisions, Industry standard simulators, Floor-planning, Modeling and simulation, Memory Logic Analog circuits, Verification processes, Placement and routing

Floorplanning and power planning, Clock tree synthesis and optimization, Routing and physical optimization, Timing closure and formal verification

hardware engineering , Verilog, Floor Planning, Timing Analysis, Physical Design, design engineering

3D Modeling, Electrical design principles, Creo, Assembly Design, Electrical Cabinet Design, Harness Routing, Rolling stock systems, Detailed drawings

layout verification , static timing analysis, Synthesis, electrical rule checking, coverage analysis, formal equivalence verification, SoC designs, physical design implementation, Power Clock Distribution, structural design checking, Place And Route, power and noise analysis, Floor Planning, RTL to GDS, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis