Routing, Perl, Python, Tcl, Physical Design Methodology, power analysis, Cadence PD Tool Flow, EM Analysis, Power Integrity Concepts, Noise Analysis, Power Rail PDN Analysis, Current Density Check, Placement, Power Gating, Logic Synthesis, Clock Tree Synthesis, Voltage Islands, IR Verification

Ecos, Python, Tcl, physical closure, CTS, Fusion Compiler, ICC2, physical design implementation, Asic Physical Design, Timing Concepts, Innovus, PD flows and methodologies

Synopsys tool suite, physical design verification, IR EM analysis and resolution, ICV or Calibre tools, block level and full-chip physical verification methodology, full chip floor-planning and integration, complete physical design flow, block subsystem timing closure

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

pipelining , rtl development , Ecos, Perl, Python, Tcl, Genus Fusion Compiler, Clock gating, Design DFT, Cadence Conformal LEC, UPF, Low-power design implementation, Cadence Conformal Low Power, MCMM synthesis, Physical Synthesis, Physical Design, STA timing closure, Multi-clock domain designs, Synopsys DCG, Synopsys Prime Time, Synthesis methodologies, Timing Constraints, formal verification

Unix, Perl, Verilog, System Verilog, Python, Tcl, Synopsys Fusion Compiler, PPA tradeoffs, Power Planning, Physical Design, Timing Closure, Innovus, Timing Power EM IR PDV

Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route