logic bist , Scan Insertion, Multi-voltage power-gated designs, Boundary scan IEEE 1149.1, FinFET nodes 7nm 5nm or below, Transition Path Delay, MBIST, Synopsys TestMAX, Scan compression, Siemens Mentor Tessent, DFT architecture, Cadence Modus, ATPG, Hierarchical DFT, Stuck-at