Verilog, Logic Design, silicon design validation, RTL blocks, design architecture spec documents, on-chip memory controller, verification processes, design simulation

layout verification , static timing analysis, Synthesis, electrical rule checking, coverage analysis, formal equivalence verification, SoC designs, physical design implementation, Power Clock Distribution, structural design checking, Place And Route, power and noise analysis, Floor Planning, RTL to GDS, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

hardware engineering , Verilog, Floor Planning, Timing Analysis, Physical Design, design engineering