Network connectivity and topology, Electric Utility Data Maintenance, GIS data modelling, GE Smallworld GIS, Ability to interpret as-built and design documents, GIS data maintenance updates and validation

Routing, Automation, HBM3, Design validation, Parasitic modeling, Placement, Tape-out revisions, Industry standard simulators, DDR5, Floor-planning, Memory Logic Analog circuits, Modeling and simulation, LPDDR6, LPDDR5

Design validation plans (DVP&R, 2D drawings, Feasibility Studies, Packaging analysis, Prototype build and testing, Tolerance stack-ups

Silicon Validation, Analog Design, automotive Ethernet, mixed-signal design, IC tape-out, Cadence Virtuoso, Spectre, layout techniques, Circuit Design

layout verification , static timing analysis, Synthesis, coverage analysis, electrical rule checking, SOC design, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, Place And Route, power and noise analysis, RTL to GDS, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis