layout verification , automation, Totem checks, Shield Matching, Layout Design, DRC, EM checks, standard cells, skill coding, auto placement and route tools, LVS

STA tools - Tempus, Static Timing Analysis, Spice to STA correlation, Physical Verification DRC LVS DFM, primetime, Placement of hard macros, Clock-tree synthesis, Routing timing optimizations, Hierarchical designs, Floorplan design, Low Power implementation, Parasitic Extraction, Congestion reduction techniques, Timing analysis validation and debug, PCIe timing closure

Test Engineering, Automation Solutions, Robotics, Machine Vision Systems, Failure Analysis