simvision , Perl, Python, Tcl, VerilogHDL, Finefet planner, Liberate, ICC2, block level timing analysis, Standard Cell design layout and verification, Solido Analytics, Siliconsmart, CMOS device physics, CMOS Circuit Design, FINESIM, primetime, Skill, HSIM, Hspice, RTL GDS flow setup, Cadence Virtuoso

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM