simvision , Python, Perl, Tcl, Standard Cell design, Finefet planner, Liberate, ICC2, Solido Analytics, AI-assisted tools, FINESIM, HSIM, lib release, DTCO development, layout and verification, VerilogHDL, block level timing analysis, Siliconsmart, CMOS device physics, CMOS Circuit Design, Skill, primetime, Hspice, RTL GDS flow setup, Cadence Virtuoso

Hdl Languages, Perl, Verilog, Python, Tcl, FPGA tools, quartus, VHDL, Vivado, systemverilog

Usb, Pcie, Ethernet, Software Engineering, FPGA Verilog design, high speed protocols, AMD Xilinx technology and tools

litmus , Tcl, Python, Innovus, Cadence EDA tools, Tempus, Certus, Conformal, Voltus, AI tools, pegasus, Genus

Vcs, Uart, Spi, Gpio, DDR, Pcie, Ethernet, I2c, System Verilog, verification tools from Synopsys, third-party VIPs, Xsim, Verification IP from Synopsys, UPF, Xprop, SOC Design Verification, MIPI, power-aware verification, HBM, CXL, Gate-level simulations, QSPI, I3C