Soc Architecture, Verilog, Cache, Logic synthesis techniques, Assertion-based formal verification, power analysis, Emulation platforms, Fabric coherence, Memory compression, FPGA design verification, systemverilog, RTL design concepts, Synthesis, Dft, Digital logic design principles, DRAM, Low-power design techniques

C, Perl, Vcs, Python, Xcelium, Uvm, systemverilog

DVCS e.g. Git, Dom, Xpath, Gcc, Xslt, Sql, Linux, Xml, Javascript, Python, System Verilog, Assembly languages, SGE or other DRMS, Uvm, Web programming – HTML, LLVM, SVA

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, formal verification, MIPI, Test Bench, transaction level modeling, AXI4

Rtos, Bash Scripting, Assembly Language, Python Programming, Emulation pre-si environment, JTAG tool debuggers, Linux kernel internals, DFT and Modem characterization, ARM SoC architecture, C Language

arm architecture , Usb, Gerrit, Uart, Spi, Silicon Validation, Git, Embedded C Programming, Debugging, I2c, Device Driver Development, low-level embedded systems, i2s, eMMC, Bare-metal programming, SoC bring-up, root-cause analysis

static timing analysis, UNIX, Linux, Perl, Verilog, Tcl, CAD software scripts, Synthesis, DFT RTL integration, Scan Insertion, Timing Analysis, ATPG verification, waveform debugging tools, Rtl Design, EDA tools methodology, test pattern generation, DFT design-for-test, equivalency checking, DFD design-for-debug, verification of DFx logic, DFT documentation, c-shell