Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route

Static Timing Analysis, Fusion Compiler, Physical Design Flow, floorplanning, ICC2, Innovus, primetime, Synthesis, Power Rail Grid Design, Mentor Graphics, Place And Route, Clock Tree Synthesis

DFT (Design for Testing), System Verilog, low power design, SOC design, Clock/Voltage Domain Crossing

Static Timing analysis, Perl, Tcl, Clock Planning, Implementation PnR Signoff, Parasitic Extraction, Floor Planning, Power Plan, Digital place and route, Constraint development, Place And Route, High speed SoC designs, Clock Tree Synthesis

Perl, Python, Tcl, floor-planning, CTS, CAD tool flow solutions, physical design concepts, EDA tool flow methodology, STA analysis, Place And Route, Physical Verification

Tcl Scripting, Static Timing Analysis, Cadence Tools, Physical Verification, Synthesis, Physical Design, DFT architectures, Backend flows, Reliability Closure