Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm

Jtag, Dft, ATPG, Scan Insertion

Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

Jtag, Shell, Python, Tcl, scan compression, IEEE 1149.x, automation infrastructure, automation and scripting, MBIST, DFT implementation methodology, IEEE 1687, DFT EDA tools, ATPG, Cad Methodology, hierarchical DFT methodologies, LBIST

boundary scan , Jtag, Perl, Shell scripting, Python, Tcl, Scan Insertion, MBIST, SMS and SEQ insertion, Multi-clock DFT architectures, Scan compression, Test clocks, Transition fault pattern generation, ATPG, Resets, DFT DRC debugging, Synopsys DFT tools, Coverage closure

DFT strategies, Tessent, ATPG pattern generation, MBIST, Cadence, Synopsys, IJTAG, Scan compression